INTRODUCTION
Nowadays, digital memories are used in each and every fields of day-to-day life. Semiconductors form the fundamental building blocks of the modern electronic world providing the brains and the memory of products all around us from washing machines to super computers. But now we are entering an era of material limited scaling. Continuous scaling has required the introduction of new materials.
Current memory technologies have a lot of limitations. The new memory technologies have got all the good attributes for an ideal memory. Among them Ovonic Unified Memory (OUM) is the most promising one. OUM is a type of nonvolatile memory, which uses chalcogenide materials for storage of binary data. The term “chalcogen” refers to the Group VI elements of the periodic table. “Chalcogenide” refers to alloys containing at least one of these elements such as the alloy of germanium, antimony, and tellurium, which is used as the storage element in OUM. Electrical energy (heat) is used to convert the material between crystalline (conductive) and amorphous (resistive) phases and the resistive property of these phases is used to represent 0s and 1s.
To write data into the cell, the chalcogenide is heated past its melting point and then rapidly cooled to make it amorphous. To make it crystalline, it is heated to just below its melting point and held there for approximately 50ns, giving the atoms time to position themselves in their crystal locations. Once programmed, the memory state of the cell is determined by reading its resistance
OVER VIEW
We are now living in a world driven by various electronic equipments. Semiconductors form the fundamental building blocks of the modern electronic world providing the brains and the memory of products all around us from washing machines to super computers. Semi conductors consist of array of transistors with each transistor being a simple switch between electrical 0 and 1. Now often bundled together in there 10’s of millions they form highly complex, intelligent, reliable semiconductor chips, which are small and cheap enough for proliferation into products all around us.
Identification of new materials has been, and still is, the primary means in the development of next generation semiconductors. For the past 30 years, relentless scaling of CMOS IC technology to smaller dimensions has enabled the continual introduction of complex microelectronics system functions. However, this trend is not likely to continue indefinitely beyond the semiconductor technology roadmap. As silicon technology approaches its material limit, and as we reach the end of the roadmap, an understanding of emerging research devices will be of foremost importance in the identification of new materials to address the corresponding technological requirements.
If scaling is to continue to and below the 65nm node, alternatives to CMOS designs will be needed to provide a path to device scaling beyond the end of the roadmap. However, these emerging research technologies will be faced with an uphill technology challenge. For digital applications, these challenges include exponentially increasing the leakage current (gate, channel, and source/drain junctions), short channel effects, etc. while for analogue or RF applications, among the challenges are sustained linearity, low noise figure, power added efficiency and transistor matching. One of the fundamental approaches to manage this challenge is using new materials to build the next generation transistors.
PRESENT MEMORY TECHNOLOGY SCENARIO
As stated, revising the memory technology fields ruled by silicon technology is of great importance. Digital Memory is and has been a close comrade of each and every technical advancement in Information Technology. The current memory technologies have a lot of limitations. DRAM is volatile and difficult to integrate. RAM is high cost and volatile. Flash has slower writes and lesser number of write/erase cycles compared to others. These memory technologies when needed to expand will allow expansion only two-dimensional space. Hence area required will be increased. They will not allow stacking of one memory chip over the other. Also the storage capacities are not enough to fulfill the exponentially increasing need. Hence industry is searching for “Holy Grail” future memory technologies that are efficient to provide a good solution. Next generation memories are trying tradeoffs between size and cost. These make them good possibilities for development.
EMERGING MEMORY TECHNOLOGIES
Many new memory technologies were introduced when it is understood that semiconductor memory technology has to be replaced, or updated by its successor since scaling with semiconductor memory reached its material limit. These memory technologies are referred as ‘Next Generation Memories”. Next Generation Memories satisfy all of the good attributes of memory. The most important one among them is their ability to support expansion in three-dimensional spaces. Intel, the biggest maker of computer processors, is also the largest maker of flash-memory chips is trying to combine the processing features and space requirements feature and several next generation memories are being studied in this perspective. They include MRAM, FeRAM, Polymer Memory Ovonic Unified Memory, ETOX-4BPC, NRAM etc. One or two of them will become the mainstream.
FUNDAMENTAL IDEAS OF EMERGING MEMORIES
The fundamental idea of all these technologies is the bistable nature possible for of the selected material. FeRAM works on the basis of the bistable nature of the centre atom of selected crystalline material. A voltage is applied upon the crystal, which in turn polarizes the internal dipoles up or down. I.e. actually the difference between these states is the difference in conductivity. Non –Linear FeRAM read capacitor, i.e., the crystal unit placed in between two electrodes will remain in the direction polarized (state) by the applied electric field until another field capable of polarizing the crystal’s central atom to another state is applied.
In the case of Polymer memory data stored by changing the polarization of the polymer between metal lines (electrodes). To activate this cell structure, a voltage is applied between the top and bottom electrodes, modifying the organic material. Different voltage polarities are used to write and read the cells. Application of an electric field to a cell lowers the polymer’s resistance, thus increasing its ability to conduct current; the polymer maintains its state until a field of opposite polarity is applied to raise its resistance back to its original level. The different conductivity States represent bits of information.
In the case of NROM memory ONO stacks are used to store charges at specific locations. This requires a charge pump for producing the charges required for writing into the memory cell. Here charge is stored at the ON junctions.
Phase change memory also called Ovonic unified memory (OUM), is based on rapid reversible phase change effect in materials under the influence of electric current pulses. The OUM uses the reversible structural phase-change in thin-film material (e.g., chalcogenides) as the data storage mechanism. The small volume of active media acts as a programmable resistor between a high and low resistance with > 40X dynamic range. Ones and zeros are represented by crystalline versus amorphous phase states of active material. Phase states are programmed by the application of a current pulse through a MOSFET, which drives the memory cell into a high or low resistance state, depending on current magnitude. Measuring resistance changes in the cell performs the function of reading data. OUM cells can be programmed to intermediate resistance values; e.g., for multistate data storage.
MRAMs are based on the magnetoresistive effects in magnetic materials and structures that exhibit a resistance change when an external magnetic field is applied. In the MRAM, data are stored by applying magnetic fields that cause magnetic materials to be magnetized into one of two possible magnetic states. Measuring resistance changes in the cell compared to a reference performs reading data. Passing currents nearby or through the magnetic structure creates the magnetic fields applied to each cell.
OVONIC UNIFIED MEMORY
Among the above-mentioned non-volatile Memories, Ovonic Unified Memory is the most promising one. “Ovonic Unified Memory” is the registered name for the non-volatile memory based on the material called chalcogenide.
The term “chalcogen” refers to the Group VI elements of the periodic table. “Chalcogenide” refers to alloys containing at least one of these elements such as the alloy of germanium, antimony, and tellurium discussed here. Energy Conversion Devices, Inc. has used this particular alloy to develop a phase-change memory technology used in commercially available rewriteable CD and DVD disks. This phase change technology uses a thermally activated, rapid, reversible change in the structure of the alloy to store data. Since the binary information is represented by two different phases of the material it is inherently non-volatile, requiring no energy to keep the material in either of its two stable structural states.
The properties of chalcogenide glasses were first explored as a potential memory technology by Stanford Ovshinsky of Energy Conversion Devices in the 1960s. In the September 1970 issue of Electronics Magazine, Gordon Moore - co-founder of Intel - published an article on the technology. However, material quality and power consumption issues prevented commercialization of the technology. More recently, interest and research have resumed as flash and DRAM memory technologies are expected to encounter scaling difficulties as chip lithography shrinks.
PRAM can be constructed in a number of different ways but there are two notable methods. In one method, diodes are used as selection elements instead of transistors. This cuts down on cost since a diode is smaller and cheaper than a transistor. Taking this one degree further, Macronix pioneered cross-point PRAM, which is composed simply of a self-aligned chalcogenide cell sandwiched between the address lines (that is, with no transistor or diode selection element). In this manner, the chalcogenide serves as the rectifying element so the low-resistance crystalline state is never used. Instead, the cell is manipulated between distinct amorphous states. This type of cell is very low cost since it only requires two masking steps.
In August of 2004, Nanochip licensed PRAM technology for use in MEMS (micro-electric-mechanical-systems) probe storage devices. These devices are not solid state. Instead, a very small platter coated in chalcogenide is dragged beneath many (thousands or even millions) of electrical probes which can read and write the chalcogenide. Hewlett-Packard's micro-mover technology can accurately position the platter to 3 nanometers so densities of more than 1 terabit per square inch will be possible if the technology can be perfected.
OUM ARCHITECTURE
A memory cell consists of a top electrode, a layer of the chalcogenide, and a resistive heating element. The base of the heater is connected to a diode. As with MRAM, reading the micrometer-sized cell is done by measuring its resistance. But unlike MRAM the resistance change is very large-more than a factor of 100. Thermal insulators are also attached to the memory structure in order to avoid data lose due to destruction of material at high temperatures.
To write data into the cell, the chalcogenide is heated past its melting point and then rapidly cooled to make it amorphous. To make it crystalline, it is heated to just below its melting point and held there for approximately 50ns, giving the atoms time to position themselves in their crystal locations.
TEST RESULTS
Test results confirmed that the insertion of a chalcogenide manufacturing flow had no effect on measured CMOS transistor parametric and did not change the total dose response of the base technology. Preliminary results on send-ahead packaged parts indicate full functionality of the 64 kbit memory arrays. Further characterization of the ADTC wafers and packaged devices from the CTCV wafers will include chalcogenide material-specific studies, such as write cycle endurance (a.k.a. “cycle life”), operating and storage temperature effects and further radiation effects tests on packaged parts, to include total dose (60Co) and heavy ion exposure. Minimum write and read cycle timing, layout spacing evaluation, data pattern insensitivity and other design related characterization will be conducted to support product optimization.
Companies working with Ovonic Unified memory have their ultimate goal to gather enough data to begin a product design targeting a 1–4 Mbit C-RAM device that is latch-up and SEU immune to greater than 120 LET and total dose hard to greater than 1 Mrad (Si), operating across the full temperature range commonly specified for space applications.
ADVANTAGES
Ø OUM uses a reversible structural phase change.
Ø Small active storage medium.
Ø Simple manufacturing process.
Ø Simple planar device structure.
Ø Low voltage single supply.
Ø Reduced assembly and test costs.
Ø Highly scalable- performance improves with scaling.
Ø Multistates are demonstrated.
Ø High temperature resistance.
Ø Easy integration with CMOS.
Ø It makes no effect on measured CMOS transistor parametric.
Ø Total dose response of the base technology is not affected.
TIMELINE
September 1966 - Stanford Ovshinsky files first patent on phase change technology
September 1970 - Gordon Moore publishes research in Electronics Magazine
June 1999 - Ovonyx joint venture is formed to commercialize PRAM technology
November 1999 - Lockheed Martin works with Ovonyx on PRAM for space applications
February 2000 - Intel invests in Ovonyx, licenses technology
December 2000 - ST Microelectronics licenses PRAM technology from Ovonyx
March 2002 - Macronix files a patent application for transistor-less PRAM
July 2003 - Samsung begins work on PRAM technology
2003 through 2005 - PRAM-related patent applications filed by Toshiba, Hitachi, Macronix, Renesas, Elpida, Sony, Matsushita, Mitsubishi, Infineon and more
August 2004 - Nanochip licenses PRAM technology from Ovonyx for use in MEMS probe storage
August 2004 - Samsung announces successful 64Mbit PRAM array
February 2005 - Elpida licenses PRAM technology from Ovonyx
September 2005 - Samsung announces successful 256Mbit PRAM array, touts 400µA programming current
October 2005 - Intel increases investment in Ovonyx
December 2005 - Hitachi and Renesas announce 1.5 volt PRAM with 100µA programming current
December 2005 - Samsung licenses PRAM technology from Ovonyx
CONCLUSION
Unlike conventional flash memory Ovonic unified memory can be randomly addressed. OUM cell can be written 10 trillion times when compared with conventional flash memory. The computers using OUM would not be subjected to critical data loss when the system hangs up or when power is abruptly lost as are present day computers using DRAM a/o SRAM. OUM requires fewer steps in an IC manufacturing process resulting in reduced cycle times, fewer defects, and greater manufacturing flexibility. These properties essentially make OUM an ideal commercial memory. Current commercial technologies do not satisfy the density, radiation tolerance, or endurance requirements for space applications. OUM technology offers great potential for low power operation and radiation tolerance, which assures its compatibility in space applications. OUM has direct applications in all products presently using solid state memory, including computers, cell phones, graphics-3D rendering, GPS, video conferencing, multi-media, Internet networking and interfacing, digital TV, telecom, PDA, digital voice recorders, modems, DVD, networking (ATM), Ethernet, and pagers. OUM offers a way to realize full system-on-a-chip capability through integrating unified memory, linear, and logic on the same silicon chip.
REFERENCES
1. www.intel.com
2. www.ovonyx.com
3. www.baesystems.com
4. www.aero.org
5. IEEE SPECTRUM, March 2003